As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. However, as the complexity of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. This difficulty arises for several reasons. First, larger integrated circuits have a very high and still increasing logic-to-pin ratio that creates a test data transfer bottleneck at the chip pins. In addition, larger circuits require a prohibitively large volume of test data that must be then stored in external testing equipment. Moreover, applying the test data to a large circuit requires an increasingly long test application time. Furthermore, present external testing equipment is unable to test such larger circuits at their speed of operation.
Integrated circuits are presently tested using a number of structured design for testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables (memory elements like flip-flops and latches) directly controllable and observable. If this can be arranged, a circuit can be treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology is scan-based testing of integrated circuits (based on scan chains). It assumes that during testing all (or almost all) memory elements are connected into one or more shift registers. A circuit that has been designed for test has two modes of operation: a normal mode and a test, or scan, mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of shift registers called scan chains. These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit, or test, responses to the test patterns. The test responses are then compared to fault-free responses to determine if the circuit under test works properly.
Some of the DFT techniques include compactors to compress the test responses from the scan chains. For a compaction method, bits stored in flip-flops have to be used. If a design has 1,000,000 flip-flops, then there are 1,000,000 input bits for the compactor. However, this does not mean that the compactor has so many inputs. Flip-flops are physically connected into scan chains. For example, the 1,000,000 flip-flops may be connected into 250 scan chains, each with 4,000 flip-flops. Thus, the compactor may have only 250 inputs, and 1,000,000 bits of information have to flow through these “ports” sequentially during 4,000 units of time (clock cycles). A general view of the compactor connected to scan chains is shown in FIG. 1. The compactor transforms these 1 million bits into a smaller amount of bits (e.g., 5,000 bits). That is, mathematically, the compactor computes a function having 1,000,000-bit argument and 5,000-bit value. These 5,000 bits (depending on implementation) may leave the compactor simultaneously (all together at the same moment), sequentially (one bit per clock cycle during 5,000 clock cycles) or under some other schedules (e.g., 10 bits per clock cycle, during 500 clock cycles). For various reasons, all practical implementations of compactors deal with very specific subclasses of above-mentioned functions. Namely, it is common practice to use functions such that each output bit is a sum (modulo 2) of some input bits (or the negation (inversion, complement) of the sum). This is why people describe compactors in terms of checksums, i.e. sums, computed for the purpose to check their inputs. Each practical particular implementation of compactors touches two parts of the problem: (i) how to choose checksums and how to build corresponding hardware in a design phase? and (ii) how to interpret values of checksums in a testing phase. In general, X-compaction technique deals with part (ii). It can be expressed as “if a checksum includes at least one X-valued bit, then the value of this checksum is not used.” However, in a particular (conventional) implementation, the X-compaction technique deals with part (i) as well. Namely, a “standard” X-compactor computes checksums by combinational circuit (i.e. without memory). Thus, in the above example with 250 scan chains, each with 4,000 flip-flops, one possible implementation of “standard” X-compactor may use circuit (containing only XOR gates) with 250 inputs and 9 outputs. This compactor computes a function with 1,000,000 inputs and 36,000 (i.e., 4,000×9) outputs, where first 9 outputs depend only on first 250 inputs, next 9 outputs depend only on next 250 inputs, and so on. This compactor works well in average. However, in the case of 2 or more X-values (unknown values) in the same group of 250 inputs, it typically fails to detect errors in the same group.
Thus, it is desirable to provide new methods for organizing and computing checksums in X-tolerant test response compaction in scan-based testing of integrated circuits.